The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a semiconductor device with vertical gates.
Recently, there has been an increasing demand for a memory device of under 40 nm dimensions to improve integration degree. Planar or recessed gate transistors used in 8 F2 or 6 F2 cell architecture have a problem in that they cannot be scaled under 40 nm dimensions, where F denotes a minimum feature size. Therefore, a dynamic random access memory (DRAM) having a 4 F2 cell architecture that can improve the integration level by about 1.5 to 2 times compared to known integration levels and have the same scaling level is desirable. Thus, a semiconductor device with vertical gates is used.
A semiconductor device with vertical gates is fabricated by forming a vertical gate electrode surrounding an active pillar region vertically extended over a semiconductor substrate, which will be referred to as active pillars, hereafter. A channel is formed in a vertical direction in the upper and lower portions of the active pillars centering around the gate electrode. The semiconductor device with vertical gates is not restricted by a channel length even if the area of the semiconductor device is decreased.
FIGS. 1A and 1B are cross-sectional views illustrating a conventional method for fabricating a semiconductor device with vertical gates.
Referring to FIG. 1A, a substrate 11 is etched using a protective layer 12 as an etch barrier to thereby form active pillars each having some of its sidewalls recessed and having a neck and a head.
Subsequently, a gate insulation layer 14 is formed on the surfaces of the active pillars 13 and the substrate 11, and then a first conductive layer is deposited and an etch process is performed to thereby form vertical gates 15 surrounding the recessed sidewalls of the active pillars 13.
Subsequently, an interlayer dielectric layer 16 is formed to gap-fill the region between the active pillars 13, and a portion of the interlayer dielectric layer 16 is recessed to expose sidewalls of the vertical gates 15.
Subsequently, a second conductive layer 17 to serve as word lines is deposited.
Referring to FIG. 1B, word lines 17A electrically connecting the vertical gates 15 are formed by performing an etch-back onto the second conductive layer 17.
The conventional technology, however, has a shortcoming where large voids (V) are formed due to the narrow space between the active pillars 13 during the deposition of the second conductive layer 17, which will serve as word lines.
The voids formed in the second conductive layer not only may make it hard to control a subsequent etch-back process but may also cause a problem that all word lines are altogether removed in severely-effected regions (for example, a region indicated by reference numeral ‘17B’).